The present invention relates to a logic synthesis apparatus and, more particularly, to a logic synthesis apparatus suitable for logic synthesis to select and set one of a plurality of technology libraries.
In logic synthesis of recent semiconductor integrated circuit design, an appropriate one of a plurality of technology libraries is selected and set in one LSI or one module as a target in order to obtain desired performance of the operation speed and power consumption.
As an application example of the plurality of technology libraries, technology libraries are individually prepared for a plurality of threshold voltages Vth and selectively used.
For example, for a part that requires a high-speed operation, logic synthesis and optimization are done by selecting and set a technology library having a cell using a low threshold voltage Vth. For a part where reduction of power consumption is necessary, a technology library having a cell using a high threshold voltage Vth is set. Alternatively, logic synthesis is performed by setting a plurality of technology libraries simultaneously, and each cell is selected using the optimization function of a logic synthesis tool.
Recent LSI products have complex specifications and a plurality of clocks and operation modes. The requirement also often changes according to the mode. Since both the high-speed operation and low power consumption are required of one product, optimization of selection of the threshold voltage Vth and selection of the technology library is necessary.
For example, when a plurality of clocks are used in a single module, a slow clock domain rarely becomes critical for the circuit operation. It is therefore preferable to arrange a cell having a high threshold voltage Vth in such a clock domain to reduce power consumption. Conventionally, however, there are the following problems in selecting technology libraries.
1) As a logic synthesis method using two technology libraries of different threshold voltages Vth, the technology libraries are selectively used for logic synthesis and logic optimization after that. As described above, it is possible to set a plurality of technology libraries simultaneously and select a cell using the optimization function of a logic synthesis tool. However, if the required specifications of the operation speed and power consumption are not satisfied, logic synthesis is done in the following two steps.
First, logic synthesis is done at once from the upper layer of the synthesis target using a technology library of high threshold voltage Vth. At this point of time, the speed constraint may not be satisfied yet. Second, logic optimization is done using the technology library of high threshold voltage Vth and that of low threshold voltage Vth. This replaces a cell of high threshold voltage Vth with a cell of low threshold voltage Vth in a path that does not satisfy the speed constraint, thereby ensuring a high operation speed.
Conventionally, however, technology library setting is uniformly executed for an entire module. For this reason, a cell using a low threshold voltage Vth may be allocated to even an unnecessary portion, resulting in an increase in power consumption.
2) When a module is divided in accordance with clock domains, some conventional methods enable to allocate a specific technology library to each clock domain by setting a technology library for each module. However, when one module includes a plurality of clock domains, it is impossible to set a technology library for each domain.
3) There is a method of executing bottom-up logic synthesis from the module of the lowermost layer. In this method, logic synthesis and optimization are performed by setting an appropriate technology library for only a module that requires a cell of low threshold voltage Vth. In the remaining modules, no technology library of low threshold voltage Vth is set. However, this method is time-consuming in overall logic synthesis and also incapable of executing sufficient optimization between the plurality of modules.
A reference that discloses a conventional logic synthesis technique will be described below.
Japanese Patent Laid-Open No. 05-274390